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Company Details:
Broadcom Corporation

Founded in 1991, Broadcom was inspired by a vision for high-speed cable and digital subscriber line (DSL) networking for the masses. Today, Broadcom solutions enable the delivery of voice, video, data and multimedia to and throughout enterprise, office, home and mobile environments. A Fortune 500 ® Company, Broadcom provides the industry''s broadest portfolio of state-of-the-art system-on-a-chip (SoC) and software solutions used in computing and networking equipment, digital entertainment and broadband access products, and high-performance mobile devices. 

As one of the world's largest fabless semiconductor companies, Broadcom designs and develops its products in labs and design centers around the world, and then works closely with independent chip-making facilities to manufacture its products. Broadcom produces nearly two billion chips annually. 

Broadcom is headquartered in Irvine, Calif. and has offices in most major cities around the world including research and development facilities in North America, Asia and Europe

Broadcom's global customer roster includes the elite of both consumer and enterprise technology brands – from computing powerhouses to major providers of networking equipment and from home entertainment and gaming systems manufacturers to mobile device and wireless providers. 

Broadcom counts among its expansive customer base a diverse group of worldwide industry leaders including Alcatel- Lucent, Amazon, Apple, Cisco, Dell, DirecTV, EchoStar, H-P, Huawei, IBM, LG Electronics, Nintendo, Nokia, Motorola, Pace, Samsung, Thomson and ZTE, among others.

Job Description:
Position : Engineer, Staff I - IC Design
Location : Bengaluru/Bangalore
Job Profile/Description :

In this role, the candidate will play a key role in designing network switching SOCs for Broadcom Corporation. The role is technically challenging and multidimensional in many ways.

We prefer an individual that can demonstrate their technical leadership skills by bringing new initiatives in an effort to improve our RTL-to-GDS design flow and engineering process. Responsibilities include the place and route implementation, STA analysis , physical verification, clock tree building.

The candidate will utilize his / her hands-on skills in the following areas to design and develop our SOCs: clock planning, power planning, circuit analysis with IR-drop, coupling, place-and-route, parasitic extraction, timing optimization, analysis etc.

You will not only tape out these chips, but also contribute to enhance our reusable methodology and flow. Additional responsibilities include interacting with the product design teams, as well as the internal IP and library groups.

Qualification : UG - Any Graduate AND PG - Any PG Course
Experience : 6 - 9 Years
Other/Special Requirements : This position requires 6 - 9 years hands on experience with physical design and analysis tools from Magma / Synopsys / Cadence.
   
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